1. Field of the Invention
The present invention relates to the technical field of phase-locked loop (PLL) and, more particularly, to a low-jitter and wide-range frequency synthesizer for low voltage operation.
2. Description of Related Art
The essential challenge on designing the phase-locked loop (PLLs) required for Application Specific Integrated Circuit (ASICs) is that a large amount of frequencies, which are widely required for various products, should be flexibly generated at first, wherein the frequencies includes the system reference frequencies required for CPUs and the reference sampling frequencies required for the video or audio analog processors.
Accordingly, the range of the frequencies provided by the designed PLLs should be wide enough. For example, the frequencies are ranged from 10 MHz to 100 MHz for the video processors, but a few hundred KHz for the audio processors. In this case, the corresponding system processors require a frequency ranging from 500 MHz to 1 GHz, thus the range of the output frequency could be up to a multiple of 3000 to 10000 (the adjustable multiple of a voltage controlled oscillator (VCO) output frequency, e.g.: 1000M/100 kHz=10000). Owing to the variety of output frequencies, different PLL should be designed for different applications. Such a manner increases not only the management problem but also the developing costs for designing and testing the PLLs. Another solution is to design a single PLL applicable to different ICs, but how to design a PLL with a wide-range operation is a big challenge.
FIG. 1 is a block diagram of a typical PLL 100. In FIG. 1, the PLL 100 includes a phase detector 110, a charge pump 120, a filter 130, a VCO 140 and a frequency divider 150. When the PLL 100 is locked, the frequency of the signal CKOUT generated by the PLL 100 is N times of the frequency of the reference signal CKREF.
When the frequency requirement is met, a further challenge is in the purity of the PLL output frequencies, i.e., the output jitters or phase noises in view of characteristic specification.
Even a PLL generates a clear, steady clock, the noises may damage the steadiness of the clock. The degree influenced by the noises can be judged by measuring the jitter amount of a PLL output. The common jitters are as follows:
1. Cycle-to-Cycle Jitter
As shown in FIG. 2, the cycle-to-cycle jitter indicates a cycle-to-cycle difference between two successive clocks. When the cycle-to-cycle jitter of a PLL reference frequency is greater than a certain degree, i.e., over the PLL hold range, it makes the PLL unlocked. Generally, the cycle-to-cycle jitter can be expressed by a root-mean-square (rms) value as follow:
      J    c    =                    lim                  n          →          ∞                    ⁢                                    1            n                    ⁢                                    ∑                              i                =                1                            n                        ⁢                                                  ⁢                                          (                                  J                  ci                                )                            2                                            =                  lim                  n          →          ∞                    ⁢                                                  1              n                        ⁢                                          ∑                                  i                  =                  1                                n                            ⁢                                                          ⁢                                                (                                                            t                      i                                        -                                          t                                              i                        -                        1                                                                              )                                2                                                    .            
2. Periodic Jitter
As shown in FIG. 3, the periodic jitter of each period indicates a phase difference between an actual clock ti and an ideal clock T of the period. When the cycle-to-cycle jitter becomes larger, the periodic jitter relatively becomes larger. With regard to designing a system timing, such as a setup time and a hold time, considering the periodic jitter is required for avoiding a clock disorder.
3. Long-Term Jitter
After the system is operated for a long time, the long-term jitter relatively generates a larger impact on the system. As shown in FIG. 4, an initial phase difference between the actual clock and the ideal clock is zero. After a long time TL, the phase difference between the actual clock and the ideal clock is referred to as the long-term jitter, which would drift the operating point of the system.
The periodic jitter is generated by the imbalance or current leakage of a charge pump, and it generates a static phase offset between an output signal and a reference signal. For deep submicron technologies, due to the process shrinkage, the current leakage is increased exponentially, and simultaneously, the VCO tuning sensitivity of a typical PLL becomes very high, which causes the periodic jitter more serious under the requirements of low voltage and wide operating range. The long-term jitter is generated by a VCO phase difference. Because of the accumulation property of the phase errors and the leading change of the last output signal along the time axis, the long-term jitter of the output signal is increasingly accumulated in every transition.
Therefore, it is desirable to provide an improved frequency synthesizer to mitigate and/or obviate the aforementioned problems.